In digital circuits, a clock signal serves as a time-synchronizing standard and sets the speed of operation of the components of the circuit. The clock signal generally consists of a regular stream of pulses having a particular shape, for example a square-shape, and a duty cycle, which is a measure of the proportion of time the clock signal is at a logic-level high compared to the period of the clock signal (the time it takes for the clock signal to complete one cycle).
For many digital circuits, it is desirable to use a clock signal having a fifty-percent duty cycle. For example, in a digital-to-analog converter circuit and a switched capacitor filter circuit, the use of a fifty-percent duty cycle clock signal will facilitate a circuit design having optimized analog characteristics. In prior art circuits, a clock signal having a fifty-percent duty cycle is generally provided using either a phase locked loop (PLL) circuit or AC coupled elements.
However, a drawback of these prior art techniques for providing a clock signal having a fifty-percent duty cycle is that they employ analog circuit elements, such as a voltage controlled oscillator or capacitors, to produce the desired clock signal. The disadvantage of using analog circuitry for this purpose is that such an implementation is generally complex to implement and sensitive to noise and temperature variations. Also, because clock signals are generally used to drive digital circuits, using the prior art analog clock generators requires the mixing of analog and digital circuitry which adds complexity to the circuit design and precludes implementing the entire circuit in an application specific integrated circuit (ASIC). Accordingly, it is desirable to provide a clock signal having a duty cycle of approximately fifty-percent using only digital circuitry.